A New CMOS Low Drop-Out Regulator with Improved PSRR

摘要

Low-dropout regulators (LDO) are widely used in electronics products due to their precision output voltage and less prone to noise. The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators. Low Drop-Out Regulators have shown advantage over its counterpart. The design of Low Drop-Out Regulators with high performance is challenging problem now-a-days. The increasing demand, however, is especially apparent in mobile battery operated products, such as cellular phones, pagers, camera recorders, laptops etc. In this paper, A CMOS Low Drop-out Regulator with improved PSRR is proposed. The proposed circuit is developed using error amplifier, subtractor circuit and PMOS as pass device. For the improvement of dc PSRR, a subtractor circuit is introduced along with two stage error amplifier with NMOS mirror load in conventional low drop-out regulator topology. The proposed circuit is simulated using TSMC 0.18μm CMOS technology process parameters. The proposed LDO has regulation range of 1.25-1.8V and for this range output voltage is 1.2V. The proposed LDO has high dc PSRR of -57.68 dB and PSRR bandwidth of 95 KHz. The performance parameters of the proposed LDO has also been compared with the existing LDO circuits available in literature and the comparison shows that the proposed LDO has wider bandwidth range of PSRR with better dc PSRR.