Design and Implementation of Low Power Small Area Digital Input/Output Cell as a Standard Cell Using 180nm Technology

摘要

The key success factor for the rapid growth of the integrated system is the use of ASIC for various system functions. Standard cell I/O contains a collection of components that are standardized at the logic or functional level. The economic and efficient accomplishment of an ASIC design depends heavily upon the choice of the I/O cell. A standard I/O cell is a small layout that functions as a building block in larger layouts (IC's). Standard cells are widely used when creating large layouts. Since the technologies change quite often there is always a need for new standard cells. As the complexity of the design continues to increase, full-custom design is no longer feasible. As the transistor is scaled down the lane, delay and power are the major problem for and below sub-micron technology. Hence there is a requirement for the highspeed and low power standard cell libraries targeting 90nm, 65nm and 45nm. As these I/O cells are very important in today's ASIC design flow there is lot of demand for library development team in VLSI industries. [1] The methodology that is adopted for the completion of this thesis is high-speed standard I/O cell development. It is shown that by using these high speed methodologies, the speed of the circuits built by using these cells are faster than the normal ones. The high- speed methodology that is given in this thesis is mainly for the layout activity, because the layout is actual physical data contribution to the cell delay. The final results of this project are efficient yet reliable library, high-speed layout design of every leaf cell contained in the library and the liberty format lib generation of the library.