A Power Saving Multiplication Algorithm

摘要

Multiplication is widely used in many applications. A number of multiplication algorithms like Booth algorithm, radix-n algorithm have been proposed in literature. This paper proposes multiplication algorithm for integers in sign magnitude notation. The magnitudes are the operands for the multiplication. The method divides the multiplier and multiplicand into slices of two bits. The partial products for all slices is calculated and added appropriately to give the result. The proposed algorithm is synthesized using Xilinx tool. An improvement in area utilization for ASIC configuration, improvement in power consumption for ASIC configuration with degradation in time is observed for the simulated algorithm. Degradation in FPGA area utilization with no change in power consumption and execution time degradation is observed. The proposed model can be extended for two's complement multiplication, floating point multiplication.