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首页> 外文期刊>Il Nuovo Cimento della Societa Italiana di Fisica, C. Geophysics and space physics >Epitaxial hybrid pixel with triggerless readout in 130 nm Cmos technology for the Micro Vertex Detector of the Panda experiment
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Epitaxial hybrid pixel with triggerless readout in 130 nm Cmos technology for the Micro Vertex Detector of the Panda experiment

机译:具有130 nm Cmos技术的无触发读数的外延混合像素,用于熊猫实验的微型顶点检测器

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The Micro Vertex Detector (MVD) is the innermost one of the Panda experiment, sitting around the beam pipe. The sensors are arranged in a barrel section with two pixel and two strip layers, and 6 forward disks with mixed pixel and microstrip sensors. For the pixel detector part, a hybrid solution with thinned epitaxial sensors was chosen. The main requirements for the readout include: a pixel size of 100·100 μm~2, an input charge measurement with 12 b that implies an amplitude resolution of 1 part out of 4096, a working frequency of 155.5 MHz, and a triggerless acquisition. The readout of the pixel detector is based on a front end chip, named Topix, that is under development. The Asic will provide the time position with a resolution of 6.43 ns and a charge measurement with a Time Over Threshold (TOT) technique; it features a matrix of 116·110 pixel cell channels and 311 Mb/s serializers as output ports. A 130 nm Cmos technology has been used to reduce the circuit size and to provide tolerance for the total dose, besides techniques against single event upset have been implemented. A Topix prototype with the full cell has been completely tested for radiation damage before and after irradiation, and a new release has been submitted to build an hybrid assembly. The stringent requirements in terms of space for the MVD lead to an architecture based on optical links. The GigaBit Transceiver (GBT) from CERN has been chosen as the baseline solution for the interface to the data acquisition. Low mass cables based on aluminium on polyimide are under development for the interconnections.
机译:微型顶点检测器(MVD)是熊猫实验的最里面的一个,位于束管周围。传感器排列在带有两个像素层和两个带状层的桶形部分中,以及6个带有混合像素和微带传感器的前向磁盘。对于像素检测器部分,选择了带有薄型外延传感器的混合解决方案。读取的主要要求包括:像素大小为100·100μm〜2、12 b的输入电荷测量(意味着4096的分辨率中有1的分辨率),155.5 MHz的工作频率以及无触发采集。像素检测器的读数基于正在开发的名为Topix的前端芯片。 Asic将通过6.43 ns的分辨率提供时间位置,并使用时间跨度(TOT)技术进行电荷测量;它具有116·110像素单元通道矩阵和311 Mb / s串行器作为输出端口。 130 nm Cmos技术已被用于减小电路尺寸并为总剂量提供耐受性,此外还实施了针对单事件不安定的技术。带有全电池的Topix原型已经在辐射前后进行了彻底的辐射损伤测试,并且已经提交了新版本以构建混合组件。 MVD在空间方面的严格要求导致了基于光链路的架构。来自CERN的GigaBit收发器(GBT)已被选作数据采集接口的基准解决方案。基于铝的聚酰亚胺低质量电缆正在开发中。

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