首页> 外文期刊>Journal of instrumentation: an IOP and SISSA journal >Development of n~+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs
【24h】

Development of n~+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

机译:开发N〜+-In-P Planar像素像素QuadSensor flip-Chiped用Fe-i4读数ASIC

获取原文
获取原文并翻译 | 示例
           

摘要

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n~+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.
机译:我们已经开发了适用于HL-LHC像素检测器的翻转芯片模块。新的耐辐射N〜+-IN-P平面像素传感器的大小为四个Fe-I4应用特定的集成电路(ASIC)(ASICS)以6英寸的晶圆布置。在Quadsensors的设计中实现了ASIC边界上像素的读数连接的变化。凸起键合技术是针对四个ASIC开发到一个Quadsensor的。碰撞键合之前,传感器和ASIC都将其稀释至150μm,并用真空chuck固定。使用无铅的障碍物焊料,我们遇到缺乏热应力处理后的大量断开凸起的缺陷,包括辐照。在凸起键合试验后,使用带有焊料通量,im依IDIUM颠簸和带有新引入的氢回流过程的障碍物的障碍物,将焊料的表面氧化视为这种缺乏症的关键来源。使用氢气流,我们建立了带有障碍颠簸的无通量凸起键合技术,适用于具有薄传感器和薄ASIC的翻转芯片模块的批量生产。

著录项

相似文献

  • 外文文献
  • 中文文献
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号