...
机译:通过测量浮栅电压了解基于浮栅型存储器件的2D材料的记忆窗口高估
Department of Materials Engineering The University of Tokyo Tokyo 113-8656 Japan;
Department of Chemistry Saitama University Saitama 338-8570 Japan;
International Center for Materials Nanoarchitectonics National Institute for Materials Science Ibaraki 305-0044 Japan;
Research Center for Functional Materials National Institute for Materials Science Ibaraki 305-0044 Japan;
Department of Materials Engineering The University of Tokyo Tokyo 113-8656 Japan;
Department of Materials Engineering The University of Tokyo Tokyo 113-8656 Japan;
2D hetero-stack; 2D materials; floating gate; floating gate voltage; non-volatile memory;
机译:基于浮栅电压轨迹的2D存储器件设计材料和器件结构设计
机译:基于n型聚合物半导体和高k聚合物栅介质的可溶液处理的低压柔性浮栅存储器
机译:P型浮栅,用于保留和改善闪存设备的P / E窗口
机译:具有大存储器窗口的ALD Ruo {Sub} 2纳米晶浮栅存储器件的高度热稳定和可重复
机译:浮栅闪存器件,使用高kappa材料作为多晶硅氧化物。
机译:用于硅纳米晶浮栅存储器的基于Hf的高k材料
机译:基于浮栅电压轨迹的2D存储器件设计材料和器件结构设计
机译:与栅极放电特性相关的浮栅的自激振荡