A 0.8-μW window SAR ADC with offset cancellation for digital DC-DC converters

摘要

This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC-DC converters. It is designed in a standard CMOS 0.18 μm process. The ADC has a dynamic reference voltage range to reduce power consumption. The auto-zero scheme of the comparator is realized internally with a preamplifier stage and a latch stage. Post-layout simulation shows that the response time of the comparator from low-to-high and high-to-low is 3.78 ns and 2.47 ns, respectively. The resolution of the proposed window SAR ADC is 7.5 mV. The ADC is fabricated as part of a digital DC-DC converter integrated circuit and measurement results show that an average power consumption of 0.8 μW is achieved. The transient time of the DC-DC converter is within 150 ns for a load current change of 495 mA.