Estimating equivalent gate input waveform for static timing analysis - coping with waveform distortion due to VDSM processes

摘要

This paper proposes a method that captures diverse input waveforms of CMOS gates for static timing analysis. Conventionally transition time is calculated as the time difference of crossing two reference voltages, and 50% crossing time is the same with that of the original waveform. But this method cannot handle the waveform diversity caused by VDSM issues, such as crosstalk, resistive shielding and inductance. The proposed method substitute equivalent gate input waveform for the reference-point-base waveform. Our method basically utilizes least square fitting, and we improve it so as to consider gate output loading. With the proposed slew calculation, we can perform accurate static timing analysis for diverse gate input waveforms in VDSM technologies.