A realization of asymmetrically faulty D-flip/flop based on power flicking reset and its application to fail-safe systems

摘要

It's generally known that most of failures in digital system are transient under the real field. It's especially important to take the counterplan against the failure of memory device, because the faulty state continues after the transient failure occurred by power line noise and so on. In this paper, we propose an architecture of asymmetrically faulty D flip/flop under the power line noise, which is based on power flicking reset circuit. In addition, we report on the fall-safe watchdog timer composed of the above-mentioned flip/flop. The full custom LSI of these circuits are designed and produced as an experiment in accordance with the CMOS 0.6 μm technology (ROHM Co., Ltd.). The results of experiment by using noise simulator shows the expected effect.