A method of estimation of digital correction coefficient of capacitor mismatch for pipeline analog-to-digital converters

摘要

An estimation method, in which digital correction coefficients due to capacitor mismatch in pipelined ADC are directly measured by the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a maximum signal-to-noise-and-distortion ratio of 56.5dB, a maximum integral non-linearity of 0.3 LSB, and a maximum differential non-linearity of 0.3 LSB using the digital calibration.