A DFT method for core-based systems-on-a-chip based on consecutive testability

摘要

In order to make SoC testable, the following three conditions have to be satisfied. 1) Cores which compose SoC themselves are testable. 2) Cores are test-accessible from outside of SoC. 3) Interconnections between cores are testable. Under the design environment for SoC, it is also important to execute test for timing faults such as delay faults as well as that for logic faults such as stuck-at faults. For that reason, it is necessary to be able to apply any test patterns consecutively by using normal operation clock (at-speed) and observe the responses consecutively. In this paper, we propose new concepts, "consecutive transparency" for cores and "consecutive testability" for SoCs, as the properties that enable the above-mentioned test access mechanism, and then we present a design for testability method to transform a given SoC into consecutively testable one.