Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

摘要

A new design methodology of high performance CMOS MPU that applies ultra-low V{sub}(TH), which is necessary to improve circuit performance with tow power supply voltage, is discussed. The multi-V{sub}(TH), the IDDQ measurement with back bias control at low temperature and △IDDQ technologies are applied in order to speed up without increasing background leakage in IDDQ test As a result, operation frequency of 64bit MPU was successfully improved 340MHz to 560MHz without lowering IDDQ quality.