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首页> 外文期刊>Current applied physics: the official journal of the Korean Physical Society >Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs
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Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs

机译:基于体FinFET的NAND型SONOS闪存阵列中沟道掺杂浓度和鳍尺寸变化对沟道电位自升的影响

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In conducting the operation of the NAND-type flash memory array, program inhibition is performed by self-boosting of the potential of the floating silicon channel. However, the high program voltage substantially affects the adjacent cells sharing either the bit-line (BL) or the word-line (WL), which results in unwanted program operation, i.e., program disturbance, in the vicinity. In this work, the dependence of self-boosting effect of the channel potential on process variables and device dimensions have been investigated by 3-D device simulation. Through a series of simulations, the process parameters and device dimensions were identified that can provide the optimum condition in self-boosting of the channel potential avoiding such disturbance. The self-boosting effect exhibited a local maximum at the channel doping concentration of 6 × 10~(17) boron atoms/cm~3 when the Si fin width was 30 nm and the channel length is 100 nm. Also, it is shown that the boosted channel potential displays monotonic increase with channel length, while it decreases monotonically as the silicon fin width becomes thicker at a given channel doping level. The interpretation of these findings utilizes the graphed results with the advanced capacitance model for a FinFET-based nonvolatile flash memory device.
机译:在进行NAND型闪存阵列的操作时,通过自增强浮动硅沟道的电势来执行编程禁止。然而,高的编程电压实质上影响共享位线(BL)或字线(WL)的相邻单元,这导致附近的不需要的编程操作,即编程干扰。在这项工作中,已通过3-D设备仿真研究了通道电势的自增强效应对过程变量和设备尺寸的依赖性。通过一系列的模拟,确定了工艺参数和器件尺寸,这些参数和器件尺寸可以在自增强通道电位时提供最佳条件,从而避免了此类干扰。当Si鳍片宽度为30nm且沟道长度为100nm时,在6×10〜(17)硼原子/ cm〜3的沟道掺杂浓度下,自增强效应表现出局部最大值。同样,示出了在给定的沟道掺杂水平下,随着硅鳍宽度变厚,升高的沟道电势随沟道长度显示单调增加,而随着沟道长度单调减小。这些发现的解释利用基于先进电容模型的图形化结果,用于基于FinFET的非易失性闪存设备。

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