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Architecture of the impulse driven processor for the brain mechanism that is made of charge transfer devices

机译:用于电荷转移装置制成的脑机制的脉冲驱动处理器的体系结构

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The impulse-driven processor (IDP) lor perception that is made of charge-coupled devices (CCDs) and floating-gate MOS FETs is proposed. The IDP is composed of the impulse decoder (ID) that generates an impulse at the matched pattern of impulses. The outputs stimulate IDs or create the connections of a following ID by using floating gate MOS memories. A loop of IDs holds a circulating impulse. The loops are linked by means of Ids. The activation disappears according to the bottom up propagation of inhibitory impulses initiated at the absence of excitatory impulse. The attachable IDs together with loops for memory control the system in which actuators are controlled by sensors.
机译:提出了由电荷耦合器件(CCD)和浮栅MOS FET制成的脉冲驱动的处理器(IDP)LOR感知。 IDP由脉冲解码器(ID)组成,其以匹配的脉冲模式产生脉冲。 输出通过使用浮动栅极MOS存储器刺激ID或创建以下ID的连接。 一个ID循环持有循环脉冲。 循环通过IDS链接。 激活根据在没有兴奋脉冲的情况下引发的抑制脉冲的自下而上的繁殖消失。 可附加ID与回路一起用于存储器控制致动器由传感器控制的系统。

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