A method for estimating and enhancing test quality using layout information - a basic method and a few examples (bridge fault Iddq test, weighted stuck-at fault coverage)

摘要

Extremely high gate count of an LSI, manufactured with a deep submicron process, has made conventional stuck-at fault model less effective. Utilization of layout information is regarded as one of essential solutions. An Iddq test for bridging faults and a weighted pin stuck-at fault model have been introduced and evaluated by using data of real products. It has been found that weighting faults by layout elements is useful for enhancing quality of test efficiently.