Prototype evaluation of a traffic Co-processor for very high-speed routers

摘要

An LSI is prototyped as a traffic management co-processor for high speed lines with having a specific high level function. In order to meet the user demand for high speed line of routers or switches, traffic control such as 'buffer management' and 'queue scheduling', should be flexibly configured to future modification as well as work at 10Gbps or higher. Processing speed, however, could become bottlenecked, and it would be too difficult to introduce a parallel processing technique for traffic control in nature. It is because dependency between consecutive packets in the same flow effects on the results of traffic control. The other bottleneck is that scheduling mechanism could not be performed on large number of queues, because packet arrival interval is quite short compared with memory access latency. In the traffic coprocessor proposed in this paper, pre-fetch mechanism and WRR/CQ mechanism are employed to solve the bottlenecks. We have designed FPGA to evaluate the hardware performance of the traffic co-processor prototype. It has functions of Classification (Marking), WRED buffer management for 64K per-flow WRR scheduling. Circuit simulation shows that the co-processor has 10Gbps packet processing capability.