Performance Analysis of Voltage-Scaled Static and Dynamic CMOS Circuits

摘要

The performance parameters viz. power, delay and area for static and dynamic CMOS circuits are investigated, to analyze their suitability in VLSI circuits in this paper. Model has been developed for static and dynamic inverter performance. The effects of voltage, technology scaling and device dimensions are studied. The results are simulated in SPICE for scaled-supply voltages in 1.25 μm and 130 nm CMOS technology nodes. A concise approach for CMOS static and dynamic circuit performance analysis is developed. An appropriate choice of logic along with voltage-scaling can lead to the design of high performance, low-power VLSI chips.