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首页> 外文期刊>Journal of instrumentation: an IOP and SISSA journal >An open-loop front-end stage with signal compression capability and improved PSRR for mini-SDD pixel detectors
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An open-loop front-end stage with signal compression capability and improved PSRR for mini-SDD pixel detectors

机译:具有信号压缩能力的开环前端级,用于迷你SDD像素检测器的PSRR改进的PSRR

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In this work we present the design and the experimental characterization of a front-end stage for X-ray pixel sensors. Our study was carried out in the framework of the DSSC detector development for the European XFEL (X-ray Free Electron Laser). The DSSC detector is going to be used in photon science applications at the European XFEL GmbH in Hamburg, Germany, and must be able to cope with an image frame rate up to 4.5 MHz. Moreover, the single photon sensitivity and a dynamic range up to 104 photons/pixel/pulse, with a photon energy of 1 keV, is required at the same time. Therefore, to achieve these requirement the front-end must provide a non-linear amplification. The non-linear response is obtained with a simple circuit that pushes the input PMOSFET into triode region as the input signal increases. However, since the readout ASIC has more than 4000 channels operating in parallel, particular care was devoted to the robustness of the implemented solution, especially with respect to power supply rejection ratio and crosstalk among channels.
机译:在这项工作中,我们介绍了X射线像素传感器的前端阶段的设计和实验表征。我们的研究是在欧洲XFEL(X射线自由电子激光器)的DSSC探测器开发的框架内进行的。 DSSC探测器将用于德国汉堡欧洲XFEL GmbH的光子科学应用中,并且必须能够应对高达4.5 MHz的图像帧速率。此外,同时需要单光子灵敏度和高达104光子/像素/脉冲的电动范围,具有1keV的光子能量。因此,为了实现这些要求,前端必须提供非线性放大。随着输入信号的增加,用简单的电路将输入PMOSFET推向三极管区域中的简单电路获得非线性响应。然而,由于读出ASIC具有超过4000个并联的通道,因此专门针对所实施的解决方案的鲁棒性,特别是关于电源排斥比和串扰之间的稳健性。

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