Realization of Schmitt Trigger for Reducing Power Consumption Using Self Controllable Voltage Level Technique

摘要

Schmitt trigger can be defined as the comparator circuit that is used to compare the input signal with the chosen threshold level. Output level relies on input state. If the input state crosses the given threshold then only the output will change. In this presented work a self controllablevoltage technique is used to design Schmitt trigger due to which leakage current and power consumption has been reduced. The Upper Self Controllable Voltage Level (U-SVL) technique reduces the total power dissipation because it employs increased supply potential and Lower Self ControllableVoltage Level (L-SVL) employs elevated ground potential. In nanoscale CMOS VLSI Systems SVL technique is used to reduce power. The tool at which the simulation has been done is cadence virtuoso at 45 nm technology.