FPGA based Accelerated Pre-Scan Method for Sensitivity Estimation of Receiver Coils using High Level Synthesis

摘要

The reconstruction accuracy of SENSE (parallel MRI technique) [1] is a strong function of accurate estimation of receiver coils sensitivity map. In conventional SENSE reconstruction, pre-scan method [1] is widely used to estimate the sensitivity profiles of receiver coils. However, in case of multiple receiver coils, additive computational cost of pre-scan method increases the total reconstruction time of SENSE reconstruction algorithm. Recently, advanced reconfigurable devices known as Field-Programmable-Gate-Arrays (FPGAs) have been used to address the computational complexity of pMRI techniques [2]. This paper proposes a new FPGA based 32-bit floating point parameterized architecture for pre-scan method using advanced high level synthesis (HLS) tool known as Vivado Design suite.