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首页> 外文期刊>Trends in Ecology & Evolution >Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study
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Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

机译:具有用于电气性能改进的线性掺杂通道的工程化双步结构SOI-TFET:2D数值模拟研究

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In this paper, a novel double-step (DS) structure tunnel field-effect transistor with a linear doping profile channel (DSS-LDC-TFET) is presented. The use of a step-shaped structure near the source/channel interface leads to the large tunneling junction area because the band-to-band tunneling of the carriers occurs perpendicularly along the conducting path in the channel. The step-shape of the channel/drain interface reduces the electric field distribution near the drain junction which helps to suppress the ambipolar behavior. Further, the DS structure of the body suppresses the ambipolar conduction due to increasing the effective length of channel area along the device. Therefore, the height of the steps in the proposed structure plays an important role in the device characteristics. The doping profile in the channel region is considered to be linear. The maximum value of the doping concentration is at the source side and linearly decreases to its minimum value along the x-axis. Numerical simulation results show that using the linear doping distribution at the channel improves device behavior through reducing the tunneling barrier width at the source/channel interface. The optimum length for the linear-doped part of the channel is selected to maximize the on-state current without degrading much the off-state current. Finally, the comparative study between DSS-LDC-TFET with the conventional silicon-on-insulator tunnel field-effect transistor is presented.
机译:在本文中,提出了一种新的双步(DS)结构隧道场效应晶体管,具有线性掺杂曲线信道(DSS-LDC-TFET)。在源/通道接口附近的使用梯度结构的使用导致大的隧穿接合区域,因为载体的带状带隧道沿沟道中的导电路径垂直而发生。通道/漏极界面的截面形状降低了漏极交界处附近的电场分布,有助于抑制余辉行为。此外,由于增加了沿着装置的沟道区域的有效长度,因此身体的DS结构抑制了非芯片导通。因此,所提出的结构中的步骤的高度在装置特征中起着重要作用。沟道区中的掺杂曲线被认为是线性的。掺杂浓度的最大值位于源极侧,并且沿X轴线线性地减小到其最小值。数值模拟结果表明,在源/通道接口处减少隧道屏障宽度,使用通道上的线性掺杂分布改善了装置行为。选择通道的线性掺杂部分的最佳长度,以最大化导通状态电流,而不会降低大量的断开状态电流。最后,提出了具有传统硅与绝缘体隧道场效应晶体管的DSS-LDC-TFET之间的比较研究。

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