Design and Performance Analysis of Nano-Scale Memristor-Based Nonvolatile Static Random Access Memory

摘要

The leakage power of SRAM (Static Random Access Memory) is effectively saved by backing up the data from SRAM during standoff condition. In this regards, a Nonvolatile 7 Transistor 1 Memristor (Nv7T1M) SRAM is designed. The store and restore operations are investigated during powerdown and power up respectively to certify the non-volatility of the SRAM. Then its various performance parameters: read and write delay, the power dissipation for store '0 and 1,' restore '0 and 1' and reset operation is evaluated along with stability margins and compared with reported datato validate our design. Results manifest an improvement of 2 orders in read delay and 4 times in write delay keeping the comparable stable margins, while the power dissipation reduced by 3 orders, 9 orders, and 3 orders for reset, store, and restore operations as compared to reported results.This design enhances the applicability of SRAM in the developing of high-performance processor and main memory.