NUCA-2A: A New Adaptive and Behavior Aware Block Placement Process

摘要

Background: The last three decades were marked by a spectacular evolution of CPUs.Both cores number on chip and shared Low Level Cache (LLC) size are increasing what makes LLCthe bottleneck's system. One major weakness of future cache memory hierarchies will be to carry outmemory blocks availability for vertical requests, with no consideration to horizontal proximity tocores. Simulations show that some LLC accesses cost more latency cycles than off-chip accesses.Objective: This paper presents a new adaptive and blocks behavior aware process, called NUCA-2A.It manages blocks in LLC in a purpose of reducing it's latency, and it's inner bandwidth, by studyingeach block's behavior, and by placing it in the most suitable location among LLC banks.Methods: LLC accesses are classified basing on each one's specific behavior. Authors establish alsoa two levels horizontal hierarchy in LLC. This work consists to place blocks in the zones that matchesthe best their behaviors.Results: In contrast to the classic S-NUCA scheme, NUCA-2A makes a reduction of up to 60,39%of global LLC latency as well as 40,74% of average inner traffic. It makes also an average speedupof 17,89 % in term of number of instructions executed by cycle.Conclusion: Behaviors study gives encouraging results. Several methods are in use in differentfields to forecast a behavior basing on previous observations. We are working on a prefetching modelthat permits blocks migration to and from privileged banks.