Implementation Analysis of Matrix Power Cipher in Embedded Systems

摘要

In this paper we present the implementation analysis of the matrix power cipher (MPC) in embedded systems. These systems have restricted computation resources, i.e. computation speed and memory. So far the question of fast ciphers construction is very actual since a lot of projects were announced to solve this problem. For example in 2000-2003 the NESSIE (New European Schemes for Integrity and Encryption) project was carried out [1]. Some block ciphers were proposed and accepted. Among them was AES-128 cipher. But nevertheless despite the possibility to transform the block cipher to stream cipher, the project authorities recognized that no one proposed stream cipher met the security and speed requirements. The other project was dedicated to fast stream cipher design and was named eStream [2]. Some solutions of fast stream ciphers were proposed and two closely related directions of investigation were determined. The first one is hardware encryption and the second one is software encryption. International Association for Cryptographic Research is organizing annual conferences: International Workshop on fast software encryption (FSE), and International Workshop on Cryptographic Hardware and Embedded Systems (CHES). The main requirements for the new cipher proposal are security and speed. It is assumed that new cipher should have a speed no less than AES-128 speed. We would like to present here a theoretical implementation analysis of new matrix power cipher in embedded systems. The components of this cipher are presented and their security is analysed in [3, 4]. This analysis is necessary to get a preliminary cipher speed data and to compare it with AES-128 speed. Since so far AES cipher is realized in a number of microprocessors using hardware co-processors, to be honest we are comparing AES implementation in ordinary AVR family microprocessors with our cipher implementation in same microprocessors. The data of AES-128 speed was taken from [5]. The speed of our cipher was estimated by counting the microprocessor operations required for cipher realization and estimating their speed in microprocessor's clock cycles. Hence the number of cycles for 1 bit can be evaluated and compared with the same figure of AES-128 realization. On the base of these data the decision can be made if it is sensible to realize the proposed matrix power cipher using other software and hardware improvements.