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Multi-task parallel collaborative design based on SoC multi-core architecture

机译:基于SoC多核架构的多任务并行协同设计

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The high efficiency is demanded in aerospace field. In the design of the control system, adopting single processor can hardly meet the demand of efficiency required. However processor array's hardware size and off-chip bus delay cannot be ignored. In order to solve the above mentioned problems, this paper is intended to study multi-task collaborative parallel design based on multi-core SOC (system on chip). Firstly, multi-core architecture based on SOC is achieved, which includes constructing two MicroBlaze cores, two ARM (advanced RISC machines) cores and designing inter-core communication, as well as designing external data collection and hardware acceleration unit based on FPGA (field programmable gate array). Secondly, collaborative parallel design in missile control system is studied. Finally, a verification platform is developed. By comparing with single core processor, it is proved that the approaches proposed have advantages over enhancing the efficiency.
机译:航空航天领域所需的高效率。 在控制系统的设计中,采用单个处理器可能几乎不符合所需效率的需求。 但是,处理器阵列的硬件大小和片外总线延迟不能忽略。 为了解决上述问题,本文旨在基于多核SoC(芯片系统)研究多任务协作并行设计。 首先,实现了基于SOC的多核架构,包括构建两个微勃朗核心,两个臂(高级RISC机器)核心和设计核心间通信,以及设计基于FPGA的外部数据收集和硬件加速单元(字段 可编程门阵列)。 其次,研究了导弹控制系统的协同平行设计。 最后,开发了验证平台。 通过与单核处理器进行比较,证明了提出的方法具有优势,优于提高效率。

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