Design and Analysis of 4-BIT SRAM using Sleepy-Stack with Keeper and Dram Using Microwind

摘要

As the technology increases the amalgamated compactness of transistor also increases. There is a demand for portable devices like mobiles, notebooks and laptops etc. For this compactness design, feature estimate is diminished by the enhanced innovation. Reduced feature size devices require low power for their activity. Diminished power supply lessens the edge voltage. Low limit gadgets have better performance yet sub-edge leakage current paramount in such a deep submicron regime. Henceforth reducing this leakage is a noteworthy incitement for architects. To explain this numerous fieldworkers have proposed divergent thoughts. In this paper we proposed 4-bit static RAM cell using sleepy-stack keeper approach and also we implemented the 4-bit DRAM. The schematic of RAMs has been developed using DSCH and its layout has been created using Micro wind.