Cascading of Compression Algorithm to Reduce Redundancy in FPGAs Configuration Bitstream -A Novel Technique

摘要

In recent times with increasing in capacity of FPGA, bitstream size of configuration file is increasing. This leads to need of more configuration memory. Also, reconfiguration time increases with increased in bitstream size. Redundant bitstream increases overheads in reconfiguration. Bitstream compression is technique to reduce redundancy in configuration bitstream. Various researchers have used existing and modified traditional lossless bitstream compression techniques. Existing studies in this field have focused on (i) small compression ratio with less decompression speed and (ii) more decompression speed compromising the compression ratio. We proposed an approach of cascading of bitstream compression algorithm to further reduce the bitstream. It is found that cascading of RLE with Arithmetic, LZW, Huffman and LZSS algorithm gives better compression ratio. Our approach of cascading of compression algorithm improves compression ration by an average of ≈ 23%.