FPGA Implementation of Image Denoiser using Dual Tree Complex Wavelet Transform (DTCWT)

摘要

Digital images are often corrupted by noise, which degrades their visual and information quality severely. Image corruption by noise may take place at any stage of its acquisition and transmission through the medium. Image denoising is an fundamental process intended to eliminate the noise from naturally contaminated images. Addressing this case many algorithms were emerged as a result of the vast research in this domain. Due an impressive capability in parallel time-frequency analysis, wavelets were proved to be a good solution to denoising problems. The wavelet techniques are very effective to remove the noise because of their capability to confine the energy of a signal in few energy transform values. The wavelet transforms are based on shrinking the wavelet coefficients. However, the Discrete Wavelet Transform (DWT) is a effective tool, it suffers with certain limitations which reduced its use in many applications. Kingsbury suggested a redundant complex wavelet transform to avoid the above limitations in standard DWT In this paper, a dual tree complex wavelet transform (DWT) based de-noising with its applications into the noise reduction for signal pre-processing is proposed. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed denoising method mainly consists of three modules: a DTCWT, a thresholding, and an inverse DTCWT modular circuits. An appropriate wavelet filters for the design and implementation on FPGA, a detailed analysis has been carried out in Matlab Simulink R2012b software using db9, sym9, coif4, bior6.8 and Farras Length-10 wavelet filter banks. In this paper Length-10 is found to be the best filter and is chosen for FPGA implementation. Two level 2D-DTCWT based image denoising has been performed using soft thresholding with wiener filter method and then the hardware software co-simulation design has been synthesized in Xilinx ISE 14.5 and implemented on spartan 3E FPGA kit. From the results, it is observed that the design consumes a total power of 3.00137 mW and operates at a frequency of 173.340MHz.