Design of Power Efficient Reversible Carry Skip Adder

摘要

Reversible computing is emerging as a promising area of technology having wide number of applications in areas of advance computing such as low power CMOS VLSI design, quantum computing, optical computing, DNA computing nanotechnology and cryptography. Reversible logic is one of the optimization methods to reduce the power dissipation which occurs due to increasing complexity of the chip when more and more devices are integrated on a single chip. With reversible logic, we are always able to reconstruct any previous computation given a description of the current state. This paper presents various designs of reversible logic gates used for reversible operations and one of the applications as carry skip adder block. This paper also proposes improved and power efficient new reversible 4*4 carry skip adder and it is demonstrated with the help of simulation results that the performance of the adder architecture designed is better not only in terms of number of transistors and garbage outputs but also power dissipation when compared to existing counterparts in literature. Simulation results reveal that the proposed carry skip adder achieves average power dissipation of 44μW which is less as compared to the existing designs.