A 171GHz harmonic-mode PLL with-14.2dBm output power in 65nm CMOS

摘要

This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171GHz provides -14.2 dBm output power and a spur level of -67.5 dBc. The PLL is built with a varactor-free 2f(O) VCO, which is tuned by varying transistor intrinsic capacitances via MOS bulk voltages.