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Graph-Grammar-Based IP-Integration (GRIP)-An EDA Tool for Software-Defined SoCs

机译:基于Graph-graffar的IP集成(GRIP)-an EDA工具用于软件定义的SOC

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In modern system-on-chip (SoC) designs, IP-reuse is considered a driving force to increase productivity. To support various designs, a huge amount of Intellectual Property (IP) hardware blocks have been developed. The integration of those IPs into an SoC may require significant effort-up to days or weeks depending on experience and complexity. This article presents a novel approach to significantly reduce the design effort to bring-up a working SoC design by automatic IP integration as part of a library-based Software-defined SoC flow. In detail, the IP-supplier prepares a HW-accelerated software library (HASL) for the SoC architect, who wants to use the IP in an SoC design. As a key point of our approach, integration knowledge is encoded in the library as a set of integration rules. These rules are defined in the machine-readable standardized IP-XACT format by the IP supplier, who has a good knowledge of the IP's hardware details. The library preparation step on the IP supplier's side is also partly automated in the proposed flow, including a partial generation of configurable HW drivers, schedulers, and the software library functions. For the SoC architect, we have developed the graph-grammar-based IP-integration (GRIP) tool. The software application is developed using the functions supplied in the HASL. According to the calls to the HASL functions, the GRIP tool automatically integrates IP-blocks using the rule information supplied with the library and runs a full Design Space Exploration. For this, the SoC architecture and rules are transformed into the graph domain to apply graph rewriting methods. The GRIP tool is model-driven and based on the Eclipse Modeling Framework. With code generation techniques, SoC candidate architectures can be transformed to hardware descriptions for the target platform. The HW/SW interfaces between SW library functions and IP blocks can be automatically generated for bare-metal or Linux-based applications.
机译:在现代片上系统(SOC)设计中,IP-Reuse被认为是提高生产率的驱动力。为了支持各种设计,已经开发了大量的知识产权(IP)硬件块。根据经验和复杂性,将这些IP的整合可能需要大量的努力 - 最多几天或数周。本文提出了一种新的方法,可以通过自动IP集成作为基于库的软件定义的SoC流程的一部分来显着降低设计努力。详细说明,IP-Ownerier为SoC Architect准备了一个HW加速的软件库(HASL),他们希望在SoC设计中使用IP。作为我们方法的关键点,集成知识在库中被编码为一组集成规则。这些规则是由IP供应商的机器可读标准化IP-XACT格式定义,谁具有良好的IP硬件详细信息。 IP供应商侧的图书馆准备步骤也在所提出的流程中是部分自动化的,包括部分生成可配置的HW驱动程序,调度仪和软件库功能。对于SoC Architect,我们开发了基于Graph-Graffar的IP集成(GRIP)工具。软件应用程序使用HASL中提供的函数开发。根据对HASL函数的调用,Grip工具使用库提供的规则信息自动集成IP块,并运行完整的设计空间探索。为此,SOC架构和规则被转换为图形域以应用图形重写方法。抓握工具是模型驱动的,并基于Eclipse建模框架。使用代码生成技术,SoC候选体系结构可以转换为目标平台的硬件描述。可以自动为裸机或基于Linux的应用程序自动生成SW库函数和IP块之间的HW / SW接口。

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