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An FPGA implementation of novel smart antenna algorithm in tracking systems for smart cities

机译:智能城市跟踪系统中新型智能天线算法的FPGA实现

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Highlights?Use mixed-Scaling-Rotation Coordinate Rotation DIgital Computer (MSR-CORDIC) in the beamforming process.?Reduce the iteration and computational complexity in calculation using modified CORDIC based on RLS algorithm.?MSR CORDIC based RLS algorithm for beamforming can realize based on HDL coding.AbstractThe area of digital signal processing (DSP) faces a great challenge in suppressing the noise and interference in the transmitting signal. A huge number of applications are in need of such control methods for good audio communication, etc., and the most widespread method for achieving this is through COordinate Rotation DIgital Computer (CORDIC) based on QRD-RLS. However, this method requires several iterations for its calculations, and therefore in order to reduce the complexity of the calculations and for faster calculation with a minimum number of iterations, a modified CORDIC based on the QRD-RLS algorithm for the purpose of beamforming is proposed in this paper and named mixed scaling rotation coordinate rotation digital computer (MSR-CORDIC). In this work, beamforming and direction of arrival (DOA) estimation will be achieved using the MSR-CORDIC and MUSIC algorithms respectively. The proposed algorithm is developed using Verilog HDL and implemented using the Xilinx field-programmable gate array (FPGA). In all cases, the proposed algorithm shows remarkable improvement compared with the conventional SCC (space code correlator) beamforming algorithm.Graphical abstractDisplay Omitted]]>
机译:<![cdata [ 突出显示 在波束成形过程中使用混合缩放旋转坐标旋转数字计算机(MSR-CORDIC)。 减少迭代和计算复杂性在计算基于RLS算法的修改CORDIC。 基于MSR CORDIC的RLS用于波束成形的RLS算法可以基于HDL编码实现。 抽象 数字信号处理区域(DSP)面临巨大挑战抑制噪音发射信号的干扰。对于良好的音频通信等,需要大量的应用程序进行这种控制方法等,并且最广泛的实现方法是通过基于QRD-RLS的坐标旋转数字计算机(CORDIC)。然而,该方法需要几个迭代的计算,因此,为了降低计算的复杂性和利用最小次数的更快计算,提出了一种基于QRD-RLS算法的用于波束成形的QRD-RLS算法的修改条件本文并命名为混合缩放旋转坐标旋转数字计算机(MSR-CORDIC)。在这项工作中,将分别使用MSR-Cordic和Music算法来实现波束成形和到达方向(DOA)估计。所提出的算法是使用Verilog HDL开发的,并使用Xilinx现场可编程门阵列(FPGA)实现。在所有情况下,与传统的SCC(空间代码相关器)波束形成算法相比,该算法显示出显着的改进。 图形抽象 显示省略 ]]>

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