WCET-Aware Dynamic Instruction Cache Locking

摘要

Caches are widely used in embedded systems to bridge the increasing speed gap between processors and off-chip memory. However, caches make it significantly harder to compute the WCET(Worst Case Execution Time) of a task. To alleviate this problem, cache locking has been proposed. We investigate the I-cache locking problem, and propose a WCET-aware, min-cut based dynamic instruction cache locking approach for reducing the WCET of a single task. We have implemented our approach and compared it with the two state-of-the-art cache locking approaches by using a set of benchmarks from the MRTC benchmark suite. The experimental results show that our approach achieves the average improvements of 41%, 15% and 7% over the partial locking approach for the 256B, 512B and 1KB caches, respectively, and 7%, 18% and 17% over the longest path based dynamic locking approach for the 256B, 512B and 1KB caches, respectively.