Twin ADSP2101 architecture for teleconferencing applications

摘要

The advent of digital signal processors has given new life to signal processing techniques. Many of these techniques are now a reality in real-time. The mathematical complexity of the algorithms decides the need for fixed or floating point architecture. The fixed-point DSPs offer cost-effective hardware at the expense of some accuracy. Though floating-point DSPs handle complex algorithms, the size of the hardware forbids its application in portable equipment. Recently, numerous digital signal processing algorithms have been developed for better performance. These algorithms demand more processing power for real-time implementation. With this in view, a twin fixed-point DSP architecture has been developed to meet the complex processing needs; it serves as a low-cost competitor for any floating-point architecture. The paper explains the hardware scheme and presents a teleconferencing application, using multi-rate filtering techniques. Some of the experimental results obtained on the hardware are also discussed.