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A Hybrid Nano/CMOS Dynamically Reconfigurable System - Part I: Architecture

机译:混合纳米/ CMOS动态可重配置系统-第一部分:体系结构

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Rapid progress on nanodevices points to a promising direction for future circuit design. However, since nanofabrication techniques are not yet mature, implementation of nanocircuits, at least on a large scale, in the near future is infeasible. To ease fabrication and overcome the problem of high defect levels in nanotechnology, hybrid nano/CMOS reconfigurable architectures are attractive choices. Moreover, if the current photolithography fabrication process can be used to manufacture the hybrid chips, the benefits of nanotechnologies can be realized today. Traditional reconfigurable architectures can only support partial or coarse-grain runtime reconfiguration due to their limited on-chip storage and long off-chip reconfiguration latency. Recent progress on nano Random Access Memories (RAMs), such as carbon nanotube-based RAM (NRAM), Phase-Change Memory (PCM), magnetoresistive RAM (MRAM), etc., provides us with a chance to realize on-chip fine-grain runtime reconfiguration. These nano RAMs have good compatibility with the current fabrication process. By utilizing them in the hybrid design, we can take advantage of both CMOS and nanotechnology, and greatly improve the logic density, resource utilization, and performance of our design. In this article, we propose a high-performance reconfigurable architecture, called NATURE, that utilizes CMOS logic and nano RAMs. An automatic design flow for NATURE is presented in Part II of the article. In NATURE, the highly dense nonvolatile nano RAMs are distributed throughout the chip to allow large embedded on-chip configuration storage, which enables fast reading and hence supports fine-grain runtime reconfiguration and temporal logic folding of a circuit before being mapped to the architecture. Temporal logic folding can significantly increase the logic density of NATURE (by over an order of magnitude for large circuits) while remaining competitive in performance and power consumption. For ease of exposition, we use NRAMs to illustrate various concepts in this article due to the excellent properties of NRAMs. However, other nano RAMs can also be used instead. Experimental results based on NRAMs establish the efficacy of NATURE.
机译:纳米器件的飞速发展为未来的电路设计指明了一个有希望的方向。然而,由于纳米制造技术尚未成熟,因此在不久的将来至少大规模地实施纳米电路是不可行的。为了简化制造并克服纳米技术中高缺陷水平的问题,混合纳米/ CMOS可重构体系结构是有吸引力的选择。此外,如果当前的光刻制造工艺可以用于制造混合芯片,那么今天就可以实现纳米技术的优势。传统的可重配置体系结构由于片上存储空间有限以及片外重配置延迟时间长,因此只能支持部分或粗粒度的运行时重配置。纳米随机存取存储器(RAM)的最新进展,例如基于碳纳米管的RAM(NRAM),相变存储器(PCM),磁阻RAM(MRAM)等,为我们提供了实现片上精细化的机会-粮食运行时重新配置。这些纳米RAM与当前的制造工艺具有良好的兼容性。通过在混合设计中利用它们,我们可以充分利用CMOS和纳米技术的优势,并大大提高设计的逻辑密度,资源利用率和性能。在本文中,我们提出了一种高性能可重配置体系结构,称为NATURE,它利用CMOS逻辑和纳米RAM。本文的第二部分介绍了NATURE的自动设计流程。在NATURE中,高密度非易失性纳米RAM分布在整个芯片上,以允许大型嵌入式芯片上配置存储,这实现了快速读取,因此支持在映射到体系结构之前对电路进行细粒度的运行时重新配置和时间逻辑折叠。时态逻辑折叠可以显着提高NATURE的逻辑密度(对于大型电路,可以提高一个数量级),同时在性能和功耗上保持竞争力。为了便于说明,由于NRAM的出色特性,我们使用NRAM来说明本文中的各种概念。但是,也可以使用其他nano RAM。基于NRAM的实验结果证明了NATURE的功效。

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