Retargetable compiled simulation of embedded processors using a machine description language

摘要

Fast processor simulators are needed for the software development of embedded processors, for HWISW cosimulation systems, and for profiling and design of application-specific processors. Such fast simulators can be generated based on the machine description language LISA. Using this language to model processor architectures enables the generation of compiled simulators on various abstraction levels, assemblers, and compiler back ends. The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language. Furthermore, the implementation of a retargetable environment consisting of compiled simulator; debugger; and assembler is presented. Measurements for a verified, cycle-based LISA model of the TI TMS32OC62x DSP show that this approach achieves between 37× and 170× higher simulation speed compared to a commercial simulator using a standard technique and the same accuracy level.