Development of a capacity analysis and planning simulation model for semiconductor fabrication

摘要

With the vast amount of capital invested in the wafer fab facility, how to effectively utilize the capacity is always a crucial challenge for semiconductor capacity planners. Currently, static capacity planning approach is widely applied to estimate the planned capacity; however, fab management believes that the ideal planned capacity is too optimistic and unachievable since many production constraints and the impact of abnormal events (e.g., machine breakdown) are not considered. Therefore, a managerial question must be solved: “What is the reasonable capacity plan?” Hence, this paper aims to develop an object-oriented capacity analysis and planning simulation (CAPS) model, which takes into account the production constraints, the operation characteristics of machine tools (e.g., multi-chamber), and the dispatching rules applied in a full-scale wafer fab. Then, capacity planners may employ CAPS model to study the impact of the available time (AT) and its fluctuation of critical machine tools to fab overall capacity and output performance (e.g., wafer out, utilization, work in process (WIP)); a reasonable planned capacity may be generated. Consequently, fab managers only need to watch attentively on the key machine tools, which will cause high impact on the throughput, and keep their promised AT level or increase AT level.