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A 3D nanoelectrokinetic model for predictive assembly of nanowire arrays using floating electrode dielectrophoresis

机译:一种使用浮动电极介电电泳的纳米尺寸阵列预测组装的3D纳米电流模型

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摘要

Floating electrode dielectrophoresis (FE-DEP) presents a promising avenue for scalable assembly of nanowire (NW) arrays on silicon chips and offers better control in limiting the number of deposited NWs when compared with the conventional, two-electrode DEP process. This article presents a 3D nanoelectrokinetic model, which calculates the imposed electric field and its resultant NW force/velocity maps within the region of influence of an electrode array operating in the FE-DEP configuration. This enables the calculation of NW trajectories and their eventual localization sites on the target electrodes as a function of parameters such as NW starting position, NW size, the applied electric field, suspension concentration, and deposition time. The accuracy of this model has been established through a direct quantitative comparison with the assembly of manganese dioxide NW arrays. Further analysis of the computed data reveals interesting insights into the following aspects: (a) asymmetry in NW localization at electrode sites, and (b) the workspace regions from which NWs are drawn to assemble such that their center-of-mass is located either in the inter-electrode gap region (desired) or on top of one of the assembly electrodes (undesired). This analysis is leveraged to outline a strategy, which involves a physical confinement of the NW suspension within lithographically patterned reservoirs during assembly, for single NW deposition across large arrays with high estimated assembly yields on the order of 87%.
机译:浮动电极介电电泳(Fe-DEP)呈现了硅芯片上纳米线(NW)阵列的可扩展组件的承诺大道,并在与传统的双电极DEP工艺相比,在限制沉积的NWS的数量时提供更好的控制。本文介绍了3D纳米电流模型,其计算在Fe-Dem构型中操作的电极阵列的影响区域内的施加的电场及其所得的NW力/速度图。这使得能够计算目标电极上的NW轨迹和它们的最终定位站点,作为诸如NW起始位置,NW尺寸,施加的电场,悬架浓度和沉积时间的参数的函数。通过与二氧化锰阵列组合的直接定量比较建立了该模型的准确性。对计算数据的进一步分析揭示了对以下几个方面的有趣见解:(a)电极位点的NW定位中的不对称性,并且(b)从中绘制NWS以组装的工作空间区域,使其质量中心位于其中心在电极间隙区域(期望)或其中一个组装电极(不希望的)的顶部。该分析利用概述了一种策略,该策略涉及组装过程中的光刻图案储存器内的NW悬架物理禁闭,用于跨大阵列的单个NW沉积,具有高估计的大会的约0.87%的顺序。

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