A DFT method for RTL data paths based on strong testability to reduce test application time

摘要

This paper proposes a non-scan DFT method based on strong testability of register-transfer level data paths to reduce test application time. The proposed test generation method for data paths is based on hierarchical test generation. In the test generation method, test vectors and a test plan are generated for each combinational hardware element of a data path. The method generates test vectors only once for combinational hardware elements consisted of the same logic circuit. These hardware elements can be tested by using the same test vectors. To reduce test application time, we test those hardware elements concurrently. We also consider testing combinational hardware elements in a pipelined fasion. The method can achieve complete fault efficiency and allows at-speed testing.