A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die

摘要

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair scheme for an embedded 6T-SRAM to achieve a KGD-SoC. We fabricated a 16M-SRAM with these techniques using 65 nm LSTP technology, and confirmed its efficient operation. The WLBI mode has almost no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy area penalty is less than 2%.