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首页> 外文期刊>電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices >Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
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Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques

机译:基于竞争减少技术的低功耗高速降时钟摆触发器

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摘要

Recently there is an increasing demand for mobile computing devices. Portable music players, multimedia mobile phone, and many other new gadgets are becoming more common in everyday life. All of these devices have many things in common, its dependency on limited battery power while required to be able to be used longer per battery recharge, its fairly limited computing power requirement (compared to conventional devices), is but a few. On the other hand, the rise of processor frequency is such that heat produced by a further rise would not be tolerable by the silicon. The afore mentioned specs dictates the needs for a specially low power circuit design, even by cutting some edges on the computing power/speed.
机译:最近,对移动计算设备的需求不断增长。便携式音乐播放器,多媒体手机和许多其他新产品在日常生活中变得越来越普遍。所有这些设备都有很多共同点,它依赖有限的电池电量,而每次充电需要能够使用更长的时间,其相当有限的计算能力要求(与传统设备相比)则很少。另一方面,处理器频率的上升使得硅无法容忍进一步上升所产生的热量。前面提到的规范指出了对特殊低功耗电路设计的需求,即使通过降低计算能力/速度的某些优势也是如此。

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