Low-power technique for CMOS logic circuits

摘要

Two techniques that can reduce active power dissipation in CMOS logic circuits have been proposed. One of them is a technique that can shorten rise and fall times of the input signal supplied to load gates by optimizing the number (m) of driver gates. Thus a short-circuit power dissipation is reduced resulting in decrease in the total active power (P{sub}T). Employing this technique, P{sub}T of the 8-bit square-root-and- divider circuit has been reduced to 1,890 μLW that is 91.2% of that of a conventional equivalent circuit. The other technique is the use of MOSFETs with higher threshold voltage except critical paths. This technique reduces P{sub}T of the 8-bit square-root-and-divider to 96.7% that of conventional equivalent circuit with minimal overhead in terms of operation speed.