200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4M bits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme

摘要

The 9.4M bits Ternary CAM device has been designed and fabricated. The performance of 200MHz/200MSPS(million searches per second) with 3.2W at 1.5V Vdd was achieved. Two new approaches were taken to achieve this performance. One is the Charge Injection Match Detect Circuits (CIMDC) for a very small swing voltage level (about 300 mV) of a match line and stable detection of it. The other is the improved Bank Selection Scheme (BSS) with the data-storing method in order to activate only the target bank where a match data is expected to be stored. The 200 MSPS is 1.6 times faster and the 3.2W is almost 1/4 less power consumption compared with the conventional design.