Multi-port-cache design with hierarchical multi-bank memory

摘要

In recent years, there has been a high demand for parallelism of computers. Large capacity and high bandwidth of the cache are needed for this demand. Therefore, we proposed to apply the Hierarchical Multi-port memory Architecture (HMA), which offers both high bandwidth and small area. In this paper, a HMA-cache-design example with 4 ports in a 0.18μm CMOS technology with 5 metal layers and an integration concept for data and instruction cache is introduced. The capacity of the banks in the design example is 1KB and the word length is 32bits. Due to chip-space limitations we had to restrict this design to 4 banks. The simulated access time of a bank in the test chip is 2.2ns. We could reduce the access time afterwards to 1.2ns by optimizing the critical path. A Unification method for instruction/data cache, which becomes possible with a small-area multi-port cache, consisting of multiple 1-port banks, is also discussed in this paper.