The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor

摘要

Synthetic Aperture Radar (SAR) is an all-weather microwave remote sensing system which is invented from the concept of creating and synthesizing a very much longer antenna aperture size with a smaller antenna aperture size by using signal processing techniques to produce a high resolution image of the measured earth's surface. Range-Doppler algorithm (RDA) is the first discovered digital processing algorithm used for the processing of SAR data and it is able to achieve block processing efficiency by using frequency domain operations in both range and azimuth directions at the same time maintaining the 1-Dimensional operation simplicity. Fast Fourier Transform (FFT) is the prerequisite in the RDA as it is used to transform the SAR data into frequency domain for match filtering operations. RDA become formidable and arduous without the use of FFT and IFFT as the majority of computation time and processing power (about 70%) in RDA are occupied by FFTs and IFFTs. Field-Programmable Gate Array (FPGA)-based SAR processing system approaches to the fast demand process of SAR data due to the hardware implementation of FPGA-based system exploit flexibility, reconfigurability, pipelining and massively parallel processing which yield in faster and cost-effective designs. On board storage of SAR data usually not feasible due to quick response demands, power consumption and space limitations of the carrier system. Thus, on-board processing capability is one of the most desired and demanded abilities in the SAR processing system. This article highlights the design and development of an FPGA-based SAR processor. An efficient reconfigurable FFT core and IFFT core have been designed and developed by using hardware description language (HDL). From the simulation results, the proposed architectures significantly reduced the usage of hardware resources in an FPGA while achieving the reasonably high processing speed and throughput rate with the reconfigurable ability.