Proposal of common processor architecture description for ASIP design automation - integration of processor and machine description for retargetable complier

摘要

In this paper, several retargetable compiler systems for embedded systems design are selected and discussed with comparison. And, the processor description is used as input both for ASIP development system, ASIPMeister (PEAS-III), and for the retargetable compiler generator. We considered and made a prototype whether the retargetable compiler generator generates GCC as its output. As a result, we could find that the processor description does not depend a particular system, and it's possible to construct the retargetable compiler generator by using such a processor description which is used for ASIPMeister (PEAS-III). We now continue to develop the compiler generator at KTL, for the future release of more stable one.