Gray-scale/color image-segmentation architecture based on cell-network

摘要

Image segmentation is the extraction process of all objects from natural input images and is the necessary first step of object-oriented image processing such as object recognization or object tracking. In this paper, we propose a highly-parallel digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network based implementation architecture in state-of-the-art CMOS technology. The proposed region-growing algorithm features high-speed processing, due to its simple structure, as well as good accuracy of segmentation results. The proposed chip architecture based on this algorithm has a regular cell network structure derived from two modules, and can execute a very high-speed massively parallel segmentation process. We designed the cell network for image segmentation in 0.35μm CMOS technology with 3 layers to achieve high pixel density, and carried out a full-custom optimization of the are of the two cell-network modules to achieve high pixel density. The area of the proposed digital architecture scales down with future CMOS technologies, and was estimated on the basis of the test-chip design. A cycle-base simulater of the architecture was used to investigate segmentation time and quality. As the result, 830×830 pixels on a chip, and a processing time less than 900μsec at 100MHz clock frequency are expected for a 45nm CMOS technology, predicted to become standard in 2010.