Double loop type PLL synthesizer driven by DDS

摘要

This paper presents a double loop type PLL synthesizer driven by a DDS for achieving low phase noise and low spurious level. Addition of a mixer and PLL synthesizer converts output signal of the synthesizer to lower frequency signal. Thus frequency division number of a main PLL synthesizer is decreased to reduce degradation of phase noise and spurious level. Also, relationships between frequency parameters and noise characteristics are described to achieve low phase noise and spurious level. A developed 1 Hz step 2GHz-band frequency synthesizer with 500MHz bandwidth achieved spurious level below -62dBc and phase noise below -87dBc/Hz at 1kHz offset.