【24h】

Design of current-mode modular programmable analog CMOS FLC

机译:电流模式模块化可编程模拟CMOS FLC设计

获取原文
获取原文并翻译 | 示例
           

摘要

One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller (FLC) chip utilized a novel Membership Function Circuit (MFC) which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm~2 in 0.35-μm CMOS technology (BSIM3v3). For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS (Fuzzy Logic Inference per Second) and power consumption is 2.5-mW.
机译:控制系统是模糊逻辑应用的活跃领域之一。在本文中,提出了一种提出的模糊逻辑控制器(FLC)芯片,该芯片利用了一种新型的隶属函数电路(MFC),可以对其进行编程。这种隶属函数具有动态范围大,驱动电流大,抗噪声能力强的特点,并且只需在IC引脚上设置一些电压即可对其进行简单地调整。控制器的每个输入都有五个隶属函数,输出有七个单例。还提出了一种适用于最小/最大值运算符的新结构,还提出了一种新的电流模式分压器电路,该电路具有非常小的面积,非常低的功耗,高速且准确的特性,与所建议的MFC兼容。该控制器是通用的两输入一输出模糊控制器,可以在0.35μmCMOS技术(BSIM3v3)的0.08mm〜2中实现。对于一般控制任务,FLC的输入输出推断是电压/电压。 FLC输出的最大延迟约为67 ns,相当于15-MFLIPS(每秒模糊逻辑推理),功耗为2.5 mW。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号