Ultra-Fine-Grained Power Gated (3:2) and (4:3) Counter Cells for Ultra-Low Power Hearing Aids

摘要

Digital hearing aids incorporate complex signal processing functional blocks for real time noise reduction. Ear hearing aid design is a challenge as size of wearable technology is decreasing while demand for performance at low power consumption is increasing. To meet these challenges, power critical blocks of such devices are custom designed. These blocks include counters and multipliers to be further used for complex digital signal processing blocks. Counters are frequently employed in a tree structured arithmetic circuits. Ultra fine-grained power gated (UFGPG) (3:2, 4:3) counter cell with minimal hardware overheads is proposed that automatically activates and deactivates the active and inactive functional part of counter in the real time. This architecture helps in reducing active mode leakage power besides reducing dynamic power. The inclusive 'Power Gating' circuit is a part of the standard cell logic and has dual role in the cell. Besides acting as a controller, it is used as a functional unit. A new methodology to block the short circuit current, during normal operation, is discussed. The proposed cells exhibit the full swing logic outputs which are necessary for drivability and for low voltage operation. Proposed (3:2) counter (1.67-MW/MHz at 1.8 V) consumes 35% less power than conventional counter. Also the (4:3) counter cell was found to be 39% power efficient against conventional counterpart. As different power saving techniques used for the proposed design are for real time, proposed architecture is suitable for digital hearing aid ASICs, which require both real time requirements as well as low power constraints.